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Quad, IEEE 802.3at/af PSE Controller
for Power-over-Ethernet
Detection and Classification Enable Register (R14h)
The Detection and Classification Enable register (R14h,
Table 22) is used to enable detection and classification
routines for the ports. On a power-up or after a reset con-
dition, if AUTO = 1, this register is set to a default value
of FFh. If AUTO = 0, it is set to 00h.
While in Auto and Semiautomatic mode, setting DET_EN_
(R14h[3:0]) and CLASS_EN_ (R14h[7:4]) to 1 enables
load detection, and classification (upon successful
detection) respectively. In manual mode, R14h works
like a pushbutton register. Setting a bit high launches a
single detection or classification cycle, and at the con-
clusion of the cycle the bit then clears. In SHDN mode,
programming this register has no effect.
Midspan Enable Register (R15h)
The Midspan Enable register (R15h, Table 23) is used
to control cadence timing (midspan) for the ports. On
a power-up or after a reset condition, this register is set
to a default value of 0000–XXXX where X is the latched-
in value of the MIDSPAN input. Setting MIDSPAN_
(R15h[3:0]) to 1 enables cadence timing where the port
backs off and waits at least 2s (min) after each failed
load detection. The IEEE 802.3at/af standard requires
a PSE that delivers power through the spare pairs (mid-
span) to have cadence timing (see the Midspan Mode
section for details).
Reserved Register (R16h)
Register R16h is at this time reserved. Writing to this
register has no effect (the address autoincrement still
updates) and any attempt to read this register returns
all zeroes.
Table 22. Detection and Classification Enable Register
ADDRESS = 14h
SYMBOL BIT NO.
TYPE
DESCRIPTION
CLASS_EN4
CLASS_EN3
CLASS_EN2
CLASS_EN1
DET_EN4
DET_EN3
DET_EN2
DET_EN1
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Enable classification on port 4
Enable classification on port 3
Enable classification on port 2
Enable classification on port 1
Enable detection on port 4
Enable detection on port 3
Enable detection on port 2
Enable detection on port 1
Table 23. Midspan Enable Register
ADDRESS = 15h
SYMBOL BIT NO.
TYPE
DESCRIPTION
Reserved
Reserved
Reserved
Reserved
MIDSPAN4
MIDSPAN3
MIDSPAN2
MIDSPAN1
7
6
5
4
3
2
1
0
—
—
—
—
R/W
R/W
R/W
R/W
Reserved
Reserved
Reserved
Reserved
Enable cadence timing on port 4
Enable cadence timing on port 3
Enable cadence timing on port 2
Enable cadence timing on port 1
37
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